Question

(final Term, Marks = , Lesson No. )

Describe amechanism by which one segment could belong to the address space of two different processes.

Answer:

Since segment tables are a collection of base–limit registers, segments can be shared when entries in the segment table of two different jobs point to the same physical location. The two segment tables must have identical base pointers, and the shared segment number must be the same in the two processes.

Question

(final Term, Marks = , Lesson No. )

Suppose we have a processor with a base CPI of 1.0 assuming all references hit in the primary (level-1) cache and a clock rate of 500 MHz. The main memory access time is 20 ns including all miss handling. Suppose the miss rate per instruction at the primary cache is 5%. How much faster will the machine be if we add a second level cache that has a 20 ns access time for either a hit or miss and is large enough to reduce the miss rate to main memory to 2%?

Answer:

Miss penalty _{main memory} = 20 x 10^-9 / (1/(500 x 10⁶)) = 10 clock cyles
CPI = Base CPI + Memory stalls per instruction
= 1.0 + (5/100) x 10 = 1.5
Miss penalty _{Level 2 cache} = 20 x 10^-9 / (1/(500 x 10⁶)) = 10 clock cyles
CPI _{with level 2 cache implemented} = Base CPI + Level 1 memory stalls + Level 2 memory stalls
= 1.0 + (5/100) x 10 + (2/100) x 10 = 1.7
Comparison = 1.7 / 1.5 = 1.13

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